A standard dynamic random access memory (DRAM) employs, as the memory cell that is formed in a large array in a silicon chip, a series combination of a switch, generally a MOSFET, and a storage capacitor in which a binary digit (bit) is stored as information for later recovery. In one form of DRAM, the storage capacitor is formed by a stack of layers over the top surface of the silicon chip with the MOSFET switch formed within a region near the top surface of the chip. A conductive plug typically provides a low resistance connection between a source/drain region of the MOSFET in the chip and the layer of the stack that serves as the lower plate (bottom electrode) of the storage capacitor.
To achieve high capacity in DRAMS it is important to make the cells small and to position them closely. It is accordingly important that the stacked capacitor in a DRAM use little surface space on the surface of the chip but still provide a sufficiently high capacitance to serve reliability as the storage node.